Principal DFT Engineer (Silicon Engineering) Jobs in USA | SpaceX Career

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

PRINCIPAL DFT ENGINEER (SILICON ENGINEERING)

Starlink has been focused on building the world’s largest constellation of satellites to provide internet to 4-bilion underserved people and bring the world closer together. The Starlink Silicon team is seeking motivated, proactive, and intellectually curious DFT engineers who can work with world-class cross-discipline teams (systems, firmware, architecture, design, validation, product engineering). In this role, you will develop silicon projects that are driving cutting-edge next-generation ASIC/FPGA designs for deployment in space and ground infrastructures.

RESPONSIBILITIES:
Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
Running and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverage
Run ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals
Run and debug non-timing and SDF annotated gate level simulations
Creating ATPG content for use in post-silicon testing and validating that content through gate level simulation
Collaborate with circuit physical design team, ATPG team and manufacturing team to facilitate high quality scan coverage in silicon

BASIC QUALIFICATIONS:
Bachelor’s degree in electrical engineering, computer engineering or computer science
10+ years of experience working with ASICs
10+ years of experience in scan insertion and DFT setup, integration and validation

PREFERRED SKILLS AND EXPERIENCE:
Understanding of ASIC design flow, methodologies, physical design, and verification
RTL experience to understand, trace and debug RTL connectivity issues as they pertain to DFT
Ability to solve complex problems including clock domain crossings and power optimization
Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience
Familiar with advanced silicon process and technology nodes for high speed and low power consumption
Experience with high reliability design and implementations
Excellent scripting skills (csh/bash, Perl, Python etc.)
Familiar with implementation or integration of design blocks using Verilog/SystemVerilog
Ability to work in a dynamic environment with changing needs and requirements
Team-player, can-do attitude, and ability to work well in a group environment while still contributing on an individual basis
Enjoys being challenged and learning new skills

ITAR REQUIREMENTS:
To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.